1. Field of the Invention
The present invention relates to liquid crystal display devices, and more particularly, to a method for fabricating a liquid crystal display panel which can simplify a fabrication process.
2. Background of the Related Art
In keeping pace with development of an information oriented society, demands on display technologies have increased in a variety of aspects. Recently, to meet the demands, different flat display technologies, such as Liquid Crystal Display (LCD) devices, Plasma Display Panel (PDP) devices, Electro Luminescent Display (ELD) devices, Vacuum Fluorescent Display (VFD) devices, and the like, have been under development. Some of these technologies are employed as display devices in various applications. Among the flat displays, LCD devices have been the most widely used as portable displays. Here, LCD devices have been replacing the CRT (Cathode Ray Tube) due to excellent picture quality, light weight, thinness, and low power consumption. In addition to portable LCD devices, such as monitors for notebook computers, LCD devices are under development for televisions and computer monitors.
Despite the various LCD technical developments on the LCD device for use in different fields, the efforts to enhance picture quality in LCD devices have been inconsistent with respect to the features and advantages of the LCD device in many aspects. Therefore, for employing the LCD device in various fields as a general display device, it is key to develop and implement high quality picture (such as high definition), high luminance, and large sized screen with light weight, thinness, and low power consumption.
The LCD device includes a liquid crystal display panel for displaying a picture, and a driving portion for providing a driving signal to the liquid crystal panel. The liquid crystal display panel has upper and lower substrates bonded with a gap therebetween, and a liquid crystal layer formed between the upper and lower substrates. The lower substrate (a thin film transistor array substrate), has a plurality of gate lines and data lines arranged intersecting each other, thin film transistors at every intersection of the gate lines and the data lines as switch devices, pixel electrodes and the like formed in an liquid crystal cell unit each connected to the thin film transistors, and an alignment film coated over the system elements. The gate lines and data lines receive scan signals and pixel voltage signals from driving circuits through relevant pads respectively. A given thin film transistor supplies a pixel voltage signal supplied to a data line to a pixel electrode in response to a scan signal supplied to a gate line. The upper substrate (a color filter array substrate) has color filters formed for each LCD cell, a black matrix for separating the color filters and reflection of an external light, a common electrode for commonly supplying a reference voltage to the LCD cells, and an alignment film coated thereon.
Fabrication of the LCD panel is finished by separately fabricating and bonding the thin film transistor array substrate and the color filter array substrate followed by injecting liquid crystal therein and sealing the substrates. In fabricating the LCD device, not one LCD panel is formed on one substrate, but rather a plurality of LCD panels are formed on a large sized substrate depending on the size of the substrate and the LCD panel.
The thin film transistor (TFT) array substrate of the LCD panel is a major portion of the cost of the LCD panel because the TFT array substrate has a complicated fabrication process including semiconductor fabrication processes and a plurality of masking processes. For solving this, fabrication processes have been developed to reduce a number of mask processes. This is because each mask process includes many processes, such as deposition, cleaning, photolithography, etching, photoresist peeling, and inspection.
A related art method for fabricating an LCD panel will be described. First, the related art TFT array substrate in the LCD panel will be described.
Referring to FIG. 1, on the lower substrate 20 (see FIGS. 2A-2D), there are gate lines 21 running in one direction in parallel at fixed intervals, a gate electrode 21a projected from the gate line 21 in one direction, and a storage lower electrode (not shown) at a position of a storage capacitor of a forward gate line. A gate pad 21b is disposed at an end of the gate line 21, and a data pad 26c is disposed at an end of the data line 26. A gate insulating film is disposed on the lower substrate 20 having the gate line 21, the gate electrode 21a, and the storage lower electrode. An active layer 25 is disposed on the gate insulating film over the gate electrode 21a. The active layer 25 is formed of amorphous silicon. Data lines 26 are formed perpendicular to the gate lines 21 to define pixel regions. A source electrode 26a projects from the data line 26 in one direction and overlaps with a portion of the active layer 25. A drain electrode 26d overlaps with the other portion of the active layer 25 spaced from the source electrode 26a. An ohmic contact layer 24a (see FIGS. 2C-2D) is disposed on the active layer 25 under the source electrode 26a and the drain electrode 26b. A storage upper electrode (not shown) is formed together with the drain electrode 26b extended to a top of the storage lower electrode formed on the forward gate line. A pixel electrode 28a contacts the storage upper electrode and the drain electrode 26b through respective contact holes in the pixel region. An organic film (not shown) is formed on an entire surface of the lower substrate 20 having the thin film transistor and the pixel region having contact holes to the gate pad 21b and data pad 26c. 
A related art method for fabricating a thin film transistor array substrate of an LCD panel will be described. FIGS. 2A-2D illustrate sections across lines I-I′, II-II′ and III-III′ in FIG. 1 showing the steps of a fabrication method.
Referring to FIG. 2A, a conductive metal is deposited on the lower substrate 20 and patterned to form a gate pad 21b having a predetermined large area at one end, a gate line extended in one direction from the gate pad 21b, and a gate electrode 21a projected in a direction from the gate line. Then, an insulating film 22, and first and second semiconductor layers (an amorphous silicon layer, and n+ doped amorphous silicon layer) 23 and 24 for forming the active layer are formed on an entire surface of the lower substrate 20 having the gate electrode 21a formed thereon in succession.
Next, referring to FIG. 2B, the first and second semiconductor layers 23 and 24 of FIG. 2A are patterned by using a mask to form an active layer 25 of an island form on the gate electrode 21a. 
Referring to FIG. 2C, a conductive metal is deposited on an entire surface of the lower substrate having the active layer 25 formed thereon and patterned to form a plurality of data lines formed in a direction perpendicular to the gate lines. Each data line has a data pad 26c at an end thereof, source electrode 26a each projected from the data line in a side direction at the gate electrode 21a, and a drain electrode 26b spaced from the source electrode 26a. In patterning the conductive metal, an ohmic contact layer 24a is formed due to over-etching of the second semiconductor layer 24 between the source electrode 26a and drain electrode 26b. Then, a protection film 27 is formed on an entire surface of the lower substrate 20 inclusive of the drain electrode 26b. 
Next, referring to FIG. 2D, the protection film 27 is etched by a photo-mask process to form first, second, and third contact holes 29a, 29b, and 29c to the drain electrode 26b, the gate pad 21b and the data pad 26c, respectively. Then, a transparent conductive metal is deposited on the protection film 27 inclusive of the first, second, third contact holes 29a, 29b and 29c, and patterned to form a pixel electrode 28a in the pixel region in contact with the drain electrode 26b through the first contact hole 29a, a gate terminal 28b on the second contact hole 29b and the protection film 27 adjacent to the contact hole 29b in contact with the gate pad 21b, and a data terminal 28c on the third contact hole 29c and the protection film 27 adjacent to the third contact hole 29c in contact with the data pad 26c. 
In above processes, five masks are used. In carrying out a pad opening process by forming the second and third contact holes 29b and 29c in the first gate pad 21b and data pad 26c, since there are two layers of the gate insulating film 22 and the protection film 27 on the gate pad 21b and only one layer of the protection film 27 on the data pad 26c, a defect is liable to occur due to a thickness difference in opening the pad. In other words, if etching is carried out until the data pad 26c is exposed, the gate pad 21b may not be opened. Thus, the use of five masks leads to a complicated fabrication process and a defective pad opening.
Consequently, a four mask fabrication process is recently introduced to reduce the number of masks. A related art method for fabricating a TFT array substrate in accordance with a four mask fabrication process will be described. FIG. 3 illustrates an enlarged plan view of a pixel on a TFT array substrate according to related art LCD, and FIG. 4 illustrates sections across lines I-I′,II-II′, and III-III′ in FIG. 3. FIGS. 5A-5D illustrate sections showing the steps of a method for fabricating a TFT array substrate shown in FIG. 4.
Referring to FIGS. 3 and 4, the TFT array substrate includes gate lines 41 and data lines 45 formed on the lower substrate 40 to cross each other with the gate insulating film 42 therebetween, a thin film transistor T formed an every intersection, a pixel electrode 49a formed in a cell region defined by the crossing structure, a gate pad 41b formed at an end of the gate line 41, and a data pad 46 at an end of the data line 45. The thin film transistor T is provided with a gate electrode 41a projected from one side of the gate line 41, a source electrode 45a projected from one side of the data line 45, a drain electrode 45b partly projected from the source electrode 45a and in contact with the pixel electrode 49a, and an active layer 43 forming a channel between the source electrode 45a and the drain electrode 45b. The active layer 43 is formed overlapping with and under the data pad 46, the data line 45, the source electrode 45a, and the drain electrode 45b. The active layer 43 further includes a channel portion between the source electrode 45a and the drain electrode 45b. The ohmic contact layer 44 is disposed on the active layer 43 for ohmic contact with the data pad 46, the data line 45, the source electrode 45a, and the drain electrode 45b. 
The thin film transistor T supplies a pixel voltage signal to the data line 45 in response to the gate signal supplied to the gate line is charged to the pixel electrode 49a. The pixel electrode 49a contacts the drain electrode 45b of the thin film transistor T through the first contact hole 48a, which passes through the protection film 47. The pixel electrode 49a causes a potential difference with a common electrode on the upper substrate (not shown) due to the charged pixel electrode. The potential difference causes the liquid crystal between the thin transistor substrate and the upper substrate to rotate by dielectric anisotropy, to transmit a light incident thereto from a light source (not shown) through the pixel electrode 49a toward the upper substrate.
The gate line 41 is connected to the gate driver (not shown) through the gate pad portion. The gate pad portion is provided with a gate pad 41b extended from the gate line 41, and a gate pad terminal 49b connected to the gate pad 41b through the second contact hole 48b passed through the gate insulating film 42 and the protection film 47. The data line 45 is connected to the data driver (not shown) through the data pad portion. The data pad portion is provided with a data pad 46 extended from the data line 45, and a pad terminal 49c connected to the data pad 46 through the third contact hole 48c passed through the protection film 47. The gate pad 41b and data pad 46 are connected to a TCP output pad (not shown) having a drive integrated circuit mounted thereon through an anisotropic conductive film.
A related art method for fabricating the foregoing TFT array substrate by using the four mask fabrication process will now be described in detail.
Referring to FIG. 5A, a gate metal layer is deposited on the lower substrate 40 by sputtering and the like, and patterned by photolithography and etching using a first mask to form a gate line 41 in one direction. A gate electrode 41a is projected from one side of the gate line 41 and a gate pad 41b at an end of the gate line 41. The gate metal layer is a single layer of Cr, Mo, or Al or a double layer.
Referring to FIG. 5B, a gate insulating film 42, an active layer 44, an ohmic contact layer 43, and data patterns are formed on the lower substrate 40 in succession inclusive of the gate patterns (gate line 41, gate electrode 41a, and gate pad 41b). Using the data portion, a data pad 46 is formed at the data pad portion. In more detail, a gate insulating film 42, an amorphous silicon layer, an n+ amorphous silicon layer, and data metal layer are formed in succession on the lower substrate 42 having gate patterns formed thereon by deposition, such as PECVD, or sputtering. A photoresist pattern is formed on a data metal layer with a second mask by photolithography. In this instance, a refractive exposure mask has a refractive exposure portion at a channel portion of the thin film transistor for making a height of the photoresist pattern at the channel portion lower than other data pattern part. Then, a wet etching is carried out using the photoresist pattern to form data patterns inclusive of the data line 45, the source line 45a, and the drain electrode 45b integrated with the source electrode 45a. Then, a dry etching is carried out using the same photoresist pattern to pattern the n+ amorphous silicon layer, and the amorphous silicon layer at the same time to form an ohmic contact layer 44 and the active layer 43. Next, the photoresist pattern having a relatively low height in the channel portion is removed by ashing, and the data pattern and the ohmic contact layer 44 are dry etched. Accordingly, the active layer 43 in the channel portion is exposed to separate the source electrode 45a and the drain electrode 45b. Then, the photoresist pattern left on the data pattern portion is removed by stripping.
In the foregoing process, the photoresist pattern is formed in the data pad portion, and the data pad 46 having the amorphous silicon layer, the n+ amorphous silicon layer, and the data metal layer stacked thereon is formed as the wet and dry etching are carried out. The gate insulating film 42 is formed of an inorganic insulating material, such as silicon oxide SiOx, or silicon nitride SiNx. The data metal layer is formed of Mo, Ti, Ta, or an Mo alloy.
Referring to FIG. 5C, a protection film 47 is formed on an entire surface of the lower substrate 40 inclusive of the data line 45 by deposition, such as PECVD or the like, and etched with a third mask by photolithography and etching to form a first to a third contact holes 48a, 48b, and 48c. The first contact hole 48a is formed to pass through the protection film 47 and expose the drain electrode 45b. The second contact hole 48b is formed to pass through the protection film and the gate insulating film 42 and expose the gate pad 41b. The third contact hole 48c is formed to pass through the protection film 47 and expose the data pad 46. The protection film 47 is formed of an inorganic insulating material, the same as the gate insulating film 42, an acryl group organic compound of a low dielectric constant, or an organic insulating material, such as BCB or PFCB, or the like.
Referring to FIG. 5D, transparent electrode patterns are formed on the protection film 47. A transparent electrode material is deposited on an entire surface of the protection film 47 by deposition, such as sputtering. Then, the transparent electrode material is patterned with a fourth mask by photolithography and etching to form transparent electrode patterns inclusive of the pixel electrode 49a, the gate pad terminal 49b, and the data pad terminal 49c. The pixel electrode 49a is electrically connected to the drain electrode 45b through the first contact hole 48a. The gate terminal 49b is electrically connected to the gate pad 41b through the second contact hole 48b. The data pad terminal 49c is electrically connected to the data pad 46 through the third contact hole 48c. 
Thus, in the related art TFT substrate and a method for fabricating the same, the employment of a four mask process permits a reduced fabrication process and saves production cost proportionately thereto as compared with the case of employing a five mask process. However, even if the thin film transistor substrate is fabricated using the four mask process, a contact hole forming process is required for opening the gate pad and the data pad formed at ends of the gate line and data line. Moreover, in formation of the contact holes, like the five mask process, even if removal of only the protection film is required in a portion over the data pad, removal of two layers of the gate insulating film and the protection film is required in a portion over the gate pad, thereby causing a defective pad opening. Thus, even if the fabrication process is simplified by reducing a number of masks, there is a problem of a defective opening in opening gate pad and data pad.